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CHAPTER 4 DESIGN OF CARRY SELECT ADDER IN 4-BIT
4.1
Carry select Adder ... 27
4.2
Conditional sum Adder ... 28
4.3
Circuit description ... 29
CHAPTER 5 SIMULATION RESULTS
5.1
Simulation results for FA ... 31
5.2
Simulation results for multi bit full Adder ... 34
CHAPTER 6 FUTURE WORK AND CONCLUSIONS
6.1
Future work ... 36
6.2
Conclusions ... 36
REFERENCES ... 37
5
LIST OF FIGURES
FIGURE NO. NAME OF THE FIGURE
PAGE NO.
2.2.1
Circuit diagram of CMOS
15
2.2.2
Schematic diagram of STA CMOS FA
16
2.3.1
Circuit diagram of PTL FA
17
2.3.2
Schematic diagram of STA PTL FA
18
2.4.1
Circuit diagram of TGA FA
19
2.4.2
Schematic diagram of STA TGA FA
20
3.1.1
Circuit diagram of 4-bit FULL ADDER
22
3.1.2
Schematic diagram of 4-bit FULL ADDER
23
3.2.1
Circuit diagram of 8-bit FULL ADDER
25
3.2.2
Schematic diagram of 8-bit FULL ADDER
26
4.1.1
Circuit diagram of 4-bit CARRY SELECT ADDER
28
4.3.1
Schematic diagram of 8-bit CARRY SELECT ADDER
30
5.1.1
Simulated I/Ps o/p waveform of FA in STA CMOS
31
5.1.2
Simulated I/Ps o/p waveform of FA in STA PTL
32
5.1.3
Simulated I/Ps o/p waveform of FA in STA TGA
32
5.2.1
Simulated I/Ps o/p waveform of 4 bit FA
34
5.2.2
Simulated I/Ps o/p waveform of 8 bit FA
35
6
LIST OF TABLES
TABLE NO. NAME OF THE TABLE
PAGE NO.
1
Truth table for 1-bit full Adder
14
2
Complete observation results of different topologies of CMOS full Adder
for different supply voltage
33
3
Comparison between 4-bit and 8-bit
35
7
LIST OF ABBREVIATIONS
CMOS
Complementary Metal Oxide Semiconductor
PMOS
P-type Metal Oxide Semiconductor
NMOS
N-type Metal Oxide Semiconductor
FA
Full Adder
STA
Static
I/N
Input
O/P
Output
INV
Inverter
PTL
Pass Transistor Logic
TG
Transmission gate
PDP
Power Delay Product
S
Sum
CO
Carry Out
CPL
Complementary pass transistor logic
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CHAPTER 1
INTRODUCTION
1.1
Introduction
The design of a Carry Select Adder is such that it operates faster than most conventional
adders. The power consumed is such an adder is also moderate and a simple gate level
modification is required of a regular CSA to reduce the power. Carry Select Adders are used for
high speed application by reducing propagation delay. Though it requires more area than most
adders but the design can be implemented in such a way that it can overcome the
aforementioned difficulties in the most suitable manner. Building low power VLSI system has
emerged as significant performance goal because of the fast technology in mobile
communication and computation. The advances in battery technology have not taken place as
fast as the advances in electronic devices. So the designers are faced with more constraints;
high-speed, high throughput and at the same time consuming as minimal power as possible.
They are likely to perpetuate the ability to further reduce the cost per function and improve the
performance of integrated circuits. The basic operation Carry Select Adder (CSA) is parallel
computation. CSA generates many carriers and partial sum [3]. The final sum and carry are
selected by multiplexers. Multiple pairs of Ripple Cary Adders (RCA) are used in CSA structure.
Hence, the CSA is not area efficient. The main goal of this Binary to Excess-1 converter (BEC)
logic is to use lesser number of logic gate than the n-bit Full Adder. The modified CSA
architecture is lower area and power consumption [10-12]. In our project, a parallel study on
different types of carry select adder in 4-bit and 8-bit has been presented. They have been
compared against various parameters like power, area and speed. Our survey includes: linear
CSA, two stage CSA, three stage CSA, CSA with sharing and SQRT CSA. In this paper, we
implement the different types of carry select adders and study the performance analysis in
terms of power, area and delay using gate level (Xilinx) and circuits level (Tanner Spice)
simulation tools. The rest of the paper is organized as follows: Section II gives a brief description
10
of different types of CSA. Section III deals with the simulation results. Section IV gives the result
analysis. Then comes the future work, followed by acknowledgement and conclusion.
Smaller feature dimension of transistors and higher level of integration have produced faster
speed, although, with increased power dissipation and power density. High power dissipation
raises temperature, degrades system reliability, and introduces high cost for heat sinks.
Numerous power management techniques targeting different components of power have been
proposed in the past few years. Examples of such techniques include clock- gating [1], gated-
ground [2], supply voltage scaling [3], and logic and architectural level techniques [4] The
relationship between dynamic/leakage power consumptions and the supply voltage (VDD) can
be summarized as [3]: 2 Dyn DD PV , S_leakDDDD ~ PVV PS_leak and PG_leak denote
dynamic power, sub-threshold leakage power and gate leakage power, respectively. Therefore,
both dynamic and leakage power can be drastically reduced by scaling down the supply voltage
[3]. 34 and DD G_leak P V e . Here PDyn, The required VDD for logic operations is mainly
determined by the required operation frequency and the critical path delay. Usually a margin is
reserved to take into account any uncertainties in circuit/device parameters and environmental
factors. However, such a worst-case-based VDD selection overestimates the actual required
VDD: the combination of worst-case conditions is rare. Carry-Select Adder (CSA) provides a
well-balanced choice between the slow speed of RCA andthe large area occupied by Carry Look-
Ahead Adder (CLA). In this paper, we propose a novel low-power Carry-Select Adder (CSA)
structure: Cascaded CSA ( 2 SA). By distinguishing between the short- and longlatency
operations, 2 SA works with variable latencies (1 or 2 cycles). Our design allows more
aggressive VDD scaling (under the same timing constraint), or extra timing margin to tolerate
the process parameter and environmental variations (under the same energy budget), while
closely maintaining the same Average Latency Per Operation (ALPO) compared to standard CSA.
Our experiments on a prototype 64-bit C2 SA show 40.7% and 44.4% total power savings in
180nm and 70nm technologies, respectively, under scaled VDDs. No ALPO-based performance
loss is introduced and only around 3.97% area overhead isincurred with respect to the standard
CSA.
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1.2
LITERATURE SURVEY
As we know adders are of fundamental importance in a wide variety of digital systems, several
types of fast adders exist but adding fast using low area and power is still challenging. In digital
adders, the speed of addition is limited by the time required to propagate a carry through
adder. So the CSLA is used in many computational systems to alleviate the problem of carry
propagation delay. So described the extremely fast digital adder with sum selection and
multiple-radix carry. He compared the amount of hardware and the logical delay for a 100-bit
ripple-carry adder and a carry-select adder. The problem of carry-propagation delay was
overcome by independently generating multiple-radix carries and using these carries to select
between simultaneously generated sums. In this adder system, the addend and augends were
divided into subaddend and subagent sections that were added twice to produce two sub sums.
One addition was done with a carry digit forced into each section, and the other addition
combined the operands without the forced carry digit. The selection of the correct sub sum
from each of the adder sections depended upon whether or not there actually was a carry into
that adder section.
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1.3
OBJECTIVES
To design full adder (FA) using different logic styles.
To design
of multi bit full adder using different logic styles
To design of carry select adder in 4-bit
1.4
THESIS OUTLINE
The Thesis is organized as follows:
Chapter 2: In this chapter 3 different full adder architecture designed and discussed.
Chapter 3: Two different multi bit FA using different logic style have been designed and
discussed in this chapter.
Chapter 4: 4-bit carry select adder designed and which has been discussed in this chapter.
Chapter 5: In this chapter simulation and performance analysis of 3 different full adder
2 different multi bit FA, 4-bit Carry select adder using Tanner13.1 EDA Tool are
discussed. Performance analysis is done with respect to average power consumed,
propagation delay, power delay product (PDP) and transistors count are discussed.
Chapter 6: Scope of future work and conclusions are discussed in this chapter.
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- , 2016, Design and Implementation of carry select adder using T-Spice, Hamburg, Bedey Media GmbH, https://www.anchor-publishing.com/document/334220
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